1. Field of the Invention
The present invention relates to semiconductor memory devices and in particular to a semiconductor memory device with hierarchized bit lines.
2. Description of Related Art
There are known technologies for hierarchizing bit lines to suppress power consumption in a semiconductor memory device. For example, Japanese Unexamined Patent Publication No. 2009-170641 (corresponding US Patent Application Publication No. 2009180306 (A1)) discloses a mask ROM (Read Only Memory) with hierarchized bit lines. With respect to this mask ROM, a method of hierarchizing bit lines and providing main bit lines and sub bit lines has been proposed to reduce the charging/discharging current of bit lines with the aim of reducing power during operation.
FIG. 1 is a circuit diagram illustrating the configuration of the semiconductor memory device disclosed in Japanese Unexamined Patent Publication No. 2009-170641. This semiconductor memory device is a mask ROM having a hierarchized bit line structure (sub bit lines and main bit lines). This semiconductor memory device includes multiple sub memory arrays SB, multiple sub bit line LB, multiple main bit lines GBL, and coupling circuits BT. Each sub memory array SB is comprised of multiple memory cells MC. The sub bit lines LB are coupled to memory cells MC. Each coupling circuit BT couples together a sub bit line LB and a main bit line GBL. The coupling circuit BT is comprised of at least one pattern in the same shape as that of each the memory cell MC.
As an example, it will be assumed that in this semiconductor memory device, one word line WL1 is selected by a row decoder 101 in read operation. Consequently, the memory cell MC111 in the sub memory array SB11 coupled to this word line WL1 and the memory cell MC211 in the sub memory array SB21 on the immediate right to the memory cell MC111. As a result, data in each memory cell MC is read to the sub bit lines LB11, LB21. When a switch transistor BT11 is thereafter selected, data on the sub bit line LB11 is transmitted to a main bit line GBL_A. Meanwhile, since a switch transistor BT21 is not selected, data read to the sub bit line LB21 is not used.